FPGA using RAM control signal lines as routing or logic resource

FPGA using RAM control signal lines as routing or logic resource

FPGA using RAM control signal lines as routing or logic...

FPGA with a plurality of input reference voltage levels

FPGA with a plurality of input reference voltage levels

FPGA with a plurality of input reference voltage levels...

FPGA with conductors segmented by active repeaters

FPGA with distributed switch matrix

FPGA with hierarchical interconnect structure and hyperlinks

FPGA with improved structure for implementing large...

FPGA with improved structure for implementing large...

FPGA with improved structure for implementing large...

Fracturable incomplete look up table area efficient logic...

Fracturable incomplete look up table for area efficient...

Fracturable lookup table and logic element

Fracturable lookup table and logic element

Fracturable lookup table and logic element

Fully programmable and configurable application specific...

Function block

Function block architecture for gate array