Fracturable incomplete look up table for area efficient...

Electronic digital logic circuitry – Multifunctional or programmable – Array

Reexamination Certificate

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C326S041000, C326S039000

Reexamination Certificate

active

06888373

ABSTRACT:
Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.

REFERENCES:
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5295090 (1994-03-01), Hsieh et al.
patent: 5349250 (1994-09-01), New
patent: 5359242 (1994-10-01), Veenstra
patent: 5359468 (1994-10-01), Rhodes et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5436575 (1995-07-01), Pedersen et al.
patent: 5481206 (1996-01-01), New et al.
patent: 5481486 (1996-01-01), Cliff et al.
patent: 5483478 (1996-01-01), Chiang
patent: 5485103 (1996-01-01), Pedersen et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5500608 (1996-03-01), Goetting et al.
patent: 5523963 (1996-06-01), Hsieh et al.
patent: 5546018 (1996-08-01), New et al.
patent: 5629886 (1997-05-01), New
patent: 5631576 (1997-05-01), Lee et al.
patent: 5672985 (1997-09-01), Lee
patent: 5675262 (1997-10-01), Duong et al.
patent: 5724276 (1998-03-01), Rose et al.
patent: 5761099 (1998-06-01), Pedersen
patent: 5818255 (1998-10-01), New et al.
patent: 5889411 (1999-03-01), Chaudhary
patent: 5898319 (1999-04-01), New
patent: 5898602 (1999-04-01), Rothman et al.
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5920202 (1999-07-01), Young et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 5999016 (1999-12-01), McClintock et al.
patent: 6021423 (2000-02-01), Nag et al.
patent: 6051992 (2000-04-01), Young et al.
patent: 6107827 (2000-08-01), Young et al.
patent: 6118300 (2000-09-01), Wittig et al.
patent: 6154052 (2000-11-01), New
patent: 6154053 (2000-11-01), New
patent: 6154055 (2000-11-01), Cliff et al.
patent: 6157209 (2000-12-01), McGettigan
patent: 6191610 (2001-02-01), Wittig et al.
patent: 6191611 (2001-02-01), Altaf
patent: 6215327 (2001-04-01), Lyke
patent: 6249144 (2001-06-01), Agrawal et al.
patent: 6288570 (2001-09-01), New
patent: 6400180 (2002-06-01), Wittig et al.
patent: 6501296 (2002-12-01), Wittig et al.
patent: 6529041 (2003-03-01), Ng et al.
E. Ahmed et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density”, FPGA 2000 Monterey Ca, pp. 3-12.
D. Cherepacha et al., “DP-FPGA: An FPGA Architecture Optimized for Datapaths”, VLSI Design 1996, vol. 4, No. 4, pp. 329-343.
S. Kaptanoglu et al., “A new high density and very low cost reprogrammable FPGA architecture”, FPGA 99 Monterey Ca, pp. 3-12.
J. Rose et al., “Architecture of Field-Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency”, J. of Solid-State circuits, vol. 25, No. 5, Oct. 1990, pp. 1217-1224.
J. L. Kouloheris et al., “FPGA Area versus Cell Granularity-Lookup Tables and PLA Cells”, FPGA '92, pp. 9-14.
“FLEX 8000 Programmable Logic Device Family”, Altera Corp. Jun. 1999, ver. 10.01, pp. 349-364.
“FLEX 10K Embedded Programmable Logic Device Family”, Altera Corp. Mar. 2001, ver. 4.1, pp. 1-28.
“FLEX 6000 Programmable Logic Device Family”, Altera Corp., Mar. 2001, ver. 4.1, pp. 1-17.
“Mercury Programmable Logic Device Family”, Altera Corp., Mar. 2002, ver. 2.0, pp. 1-34.
“APEX 20K Programmable Logic Device Family”, Altera Corp., Feb. 2002, ver. 4.3, pp. 1-29.
“Stratix FPGA Family Data Sheet”, Altera Corp., Preliminary Information, Dec. 2002, ver. 3.0, pp. 1, 11-19.
“Virtex™—II Platform FPGAS: Detailed Description”, XILINX , Advance Product Specification, v2.1.1, Dec. 6, 2002, 40 pgs.
“Orca® Series 2 Field-Programmable Gate Arrays,” Lattice, Corp. Jan. 2003, pp. 1-25.

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