FPGA with distributed switch matrix

Details FPGA with distributed switch matrix FPGA with distributed switch matrix

1993-02-19

1995-03-07

Westin, Edward R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 39, H03K 19173

Patent

active

053961269

ABSTRACT:
A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors, referred to as "Switching R-nodes". The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors to other selected ones of the (e.g., vertical) routing conductors. In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.

REFERENCES:
patent: 4870302 (1989-09-01), Freeman
patent: 5144166 (1992-09-01), Camarota
patent: 5204556 (1993-06-01), Shankar
patent: 5225203 (1993-10-01), Agrawal
patent: 5323069 (1994-06-01), Smith
patent: 5327023 (1994-07-01), Kawana et al.
"Fully Configurable Versatile Field Programmable Function Element", by Dwight D. Hill, Application filed Apr. 2, 1991, Ser. No. 07/679370.
Paper handed out at the Second International Workshop on Field Programmable Logic and Applications, "A New Architecture for High-Performance FPGAs," by D. D. Hill et al., Vienna, Austria, Aug. 31, 1992.

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