Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-11-23
2001-10-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S039000
Reexamination Certificate
active
06297666
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention (Technical Field)
The present invention relates to the field of integrated circuits, particularly field programmable gate arrays and application specific integrated circuits.
2. Background Art
Application Specific Integrated Circuits (ASICs) provide electronic designers with the ability to customize circuits by integrating complex functionality and input/output (I/O) on a single integrated circuit (IC). Field Programmable Gate Arrays (FPGAs) provide electronic designers with similar capabilities, and additionally allow functions and I/O to be programmed rather than fixed during production. The ability to program has the advantage of providing design flexibility and faster implementation during the system development effort. Furthermore, for low volumes and prototyping, an FPGA has a lower unit cost than an ASIC. Although FPGAs are flexible, allow for faster implementation, and have low unit costs, there are limits to the function complexity and the I/O capability.
Other inventions have attempted to address configuration problems existing in integrated circuits. However, none address the problem of assigning any signal to any device's pin, or lead, with selectable I/O electrical characteristics (hereinafter “pin” and “lead” shall each be understood to encompass the other). Furthermore, none disclose the ability to program power and ground to any device's lead. U.S. Pat. No. 5,705,938, to Kean, entitled “Programmable Switch for FPGA Input/Output Signals,” discloses device pins that are usable once the FPGA has been programmed instead of having dedicated programming pins. However, in this invention, the power and ground pins are still dedicated and not configurable. PCT Application Publication No. WO98/13938, to Xilinx, Inc., entitled “Integrated Circuit with Field Programmable and Application Specific Logic Areas,” discloses routing any signal to any input/output pad. However, the technology never discloses the ability to select electrical characteristics of the pad or allowing any of the pads to take on power and ground characteristics. PCT Application Publication No. WO95/16993, to Lattice Semiconductor Corporation, entitled “Application Specific Modules in a Programmable Logic Device,” discloses programming an input/output cell, but the input/output cell is limited to being defined as input, output, and bi-directional. The input/output cell is not described as taking on power and ground electrical characteristics. U.S. Pat. No. 5,825,202, to Tavana et al., entitled “Integrated Circuit with Field Programmable and Application Specific Logic Areas,” combines FPGA with “application specific logic area” to provide flexible functionality with user defined functionality on the same die. This patent does not discuss the input/output for the IC or flexibility of the input/output. U.S. Pat. No. 4,896,296, to Turner et al., entitled “Programmable Logic Device Configurable Input/Output Cell” discloses adding in-system programming capability to a PLD as well as allowing the PLD to be configured with a non-volatile switch or memory element. Unlike the present invention, the I/O cell in this patent is not designed so that a pin can take on varying electrical characteristics.
U.S. Pat. No. 5,867,037, to Capps, Jr. et al., entitled “Method and Apparatus of Programming FPGA Devices Through ASIC Devices,” discloses a mechanism to program FPGAs using an ASIC and does not describe programmability features of the input/output. U.S. Pat. No. 5,844,917, to Salem et al., entitled “Method for Testing Adapter Card ASIC Using Reconfigurable Logic,” discloses a method to test an ASIC using an FPGA. U.S. Pat. No. 5,841,790, also to Salem et al., entitled “Apparatus for Testing an Adapter Card ASIC with Reconfigurable Logic,” discloses an apparatus to test an ASIC using an FPGA. U.S. Pat. No. 5,821,776, to McGowan, entitled “Field Programmable Gate Array with Mask Programmed Analog Function Circuits,” extends FPGA technology to include analog functions with digital functions, all in a single FPGA device. I/O pads can be interconnected to either a digital function or an analog function, but not extending the interconnect to include power and ground. U.S. Pat. No. 5,765,027, to Want et al., entitled “Network Controller Which Enables the Local Processor to have Greater Access to at least One Memory Device than the Host Computer in Response to a Control Signal,” discloses an application of an ASIC/FPGA in a networking system. U.S. Pat. No. 5,687,325, to Chang, entitled “Application Specific Field Programmable Gate Array,” ties together specific digital function with a general purpose FPGA. This patent does not disclose configurable I/O or selectable electrical characteristics.
An article authored by D. Bursky, entitled “Programmable Arrays Mix FPGA and ASIC Blocks,” published in
Electronic Design
, Vol. 44, No. 21, pp. 60-70, 72, 74, describes the need for more efficient FPGA architectures to produce small chips, but does not mention configurable input/output or selectable electrical characteristics. An article authored by W. Miller, entitled ASIC Core in FPGA Integration, published in
Electronic Industry
, Vol. 28, No. 8, p. 36-38, 40, describes a product that has FPGA technology with pre-defined logic blocks, in other words, pre-defined functionality, but does not mention configurable I/O or selectable electrical characteristics.
U.S. Pat. No. 5,874,834, to New, entitled “Field Programmable Gate Array with Distributed Gate-Array Functionality,” discloses pre-defined functions in a sea-of-gates gate array, but does not mention configurable input/output or selectable electrical characteristics. U.S. Pat. No. 5,815,405, to Baxter, entitled “Method and Apparatus for Converting a Programmable Logic Device Representation of a Circuit into a Second Representation of the Circuit,” discloses how to convert representations of a circuit from one form to another for PLDs. U.S. Pat. No. 5,682,107, to Tavana et al., entitled “FPGA Architecture with Repeatable Tiles Including Routing Matrices and Logic Matrices,” refines FPGA architecture but does not have configurable I/O. U.S. Pat. No. 5,640,107, to Kruse, entitled “Method for In-Circuit Programming of a Field-Programmable Gate Array Configuration Memory,” discloses a method for reprogramming an FPGA when it is in a circuit as opposed to programming the device separately, but does not disclose configurable input/output or selectable electrical characteristics. U.S. Pat. No. 5,550,839, to Buch et al., entitled “Mask-Programmed Integrated Circuits Having Timing and Logic Compatibility to User-Configured Logic Arrays,” discloses the ability to produce mask programmable devices from FPGAs without the need for simulating the logic and timing to verify that the mask programmable device will operate once produced. An article by E. H. Stoops, entitled “Programmable Architectural Array,” published in
The IBM Technical Disclosure Bulletin
, Vol. 19, No. 12, May 1977, discloses a mechanism for being able to program a function into a chip, which is a precursor to the FPGA. However, the article does not mention configurable I/O or selectable electrical characteristics. The abstract to Japanese Patent 06-275718, to Takeo Niifuna, entitled “Gate Array Circuit,” discloses a means for having dedicated functions and programmable functions on a single chip, but not configurable I/O or selectable electrical characteristics.
The present invention solves the I/O limitation problem of ICs. This is important because electronic designers need the ability to provide for a pin-for-pin compatible IC for an existing IC in a system. This capability is necessary because manufacturers of ICs routinely make them obsolete for various reasons over time. When a manufacturer makes an IC obsolete, electronic designers who use that IC have no other option than to redesign the system, buy a lifetime supply of ICs, or design a compatible ASIC. All of these options are expensive, and a compatible ASIC is particularly expensive in low volume situ
Espelien Mark A.
Short Paul J.
Weingartner Thomas A.
Woods Jordon W.
InnoVasic, Inc.
Mays Andrea L.
Myers Jeffrey D.
Tokar Michael
Tran Anh Q.
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