Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2000-09-15
2001-10-16
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06304103
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of Field Programmable Gate Arrays and more specifically to an increase in the efficiency of signal line usage in an FPGA by employing RAM control lines as routing or logic resources after these lines are used to program control memory.
2. Prior Art
In a SRAM-programmed Field Programmable Gate Array (FPGA) a large proportion of the available metal planes are used by bit line and word line signals required for programming the control memory. In one commercial device approximately one-half of the total available routing resources on the second metal layer are used by RAM bit lines and of the remaining area a proportion is required by power and ground distribution. Numerically, there are 10 user signals routed from east to west on second metal in a unit tile and 16 RAM bit lines. The situation in the north/south direction is less serious with 12 user signals and 3 RAM word lines, but RAM signals still use a significant proportion of the available resources. After configuration of the device, the state of the RAM control memory is often not changed and these control signals are normally unused. A technique which could make use of these expensive resources for routing or logic within user designs would have considerable benefits. The techniques described here are most applicable to an FPGA where the control memory is partitioned into many smaller memories and the device can tolerate random values in its control memory without causing contention on tri-state routing resources. Such an FPGA is disclosed in British Pat. Application No. 9604496.1 filed on Mar. 1, 1996 and entitled “EMBEDDED MEMORY FOR FIELD PROGRAMMABLE GATE ARRAY”. These techniques are also applicable to blocks of embedded RAM within a more conventional FPGA. The Programmable Logic Data Book published in 1996 by Xilinx, Inc., contains relevant information and is incorporated herein by reference. Other relevant information may be obtained from the following:
1) “Semiconductor Memories”, Betty Prince, Wiley 1991.
2) “The Design of a New FPGA Architecture”, Anthony Stansfield and Jan Page in Lecture Notes in Computer Science 975, Springer Verlog 1995;
3) U.S. patent application Ser. No. 08/460,314 filed on Jun. 2, 1995 by inventor Steven Churcher and entitled “Sense Amplifier For Reading Logic Devices”.
The latter reference discloses a preferred sense amplifier for use in the present invention and is therefore incorporated herein by reference.
SUMMARY OF THE INVENTION
Use Of Ram Bit Lines As Routing Resources
A RAM bit line is a metal segment like any other metal segment on the device and can therefore be used as a routing signal line. This has not been done in previous FPGA's because of the logical separation in designers' minds between “RAM control” signals like bit lines and “user logic” signals. According to the invention, RAM bit lines are reused after configuration as signal routing lines. Precautions must be taken when using the lines as a routing resource that the RAM cells attached to the bit line are not disturbed. This can easily be achieved by ensuring that all the RAM word lines are at 0 volts except during device programming—this is normally the case in current FPGA's. To use RAM bit lines as a routing resource all that is required is to install a second driver circuit at the opposite end of the bit line from the sense amplifier and/or a duplicate sense amplifier to allow routing in the opposite direction. It must also be possible to disable the routing resource driver circuits on the bit lines during device programming. Because RAM bit lines have a relatively high capacitive load it may be desirable to use a sense amplifier to sense signals being transferred on them to increase speed. In many cases sense amplifiers will already be provided at one end of the RAM bit line for use by the programming circuitry during memory reads.
Use Of Ram Bit Lines To Implement Wide Wire-Or Functions
Perhaps more attractive than the use of bit lines as conventional routing segments, is their use to implement wire OR functions. In this case, pull down devices are placed at many locations along a RAM bit line. These pull downs are controlled by the logical AND of three signals—an enable signal that indicates the bit lines are not needed for device programming; a local memory cell output which indicates that a particular signal should take part in the wire OR; and a local logic signal (e.g. the output of a cell function unit). The state of the wire is sensed by a sense amplifier at the edge of the array in the same way as a conventional RAM cell. The output of the sense amplifier must be selectable as an input on a user routing multiplexer.
Use Of Ram Bit And Word Lines To Implement Pal Functions
A programmable array logic (PAL) AND/OR structure can be built using RAM cells as control memory. Each product term is a wire NOR function. RAM cells select the sets of input variables. Bit line signals and product terms may share a single wire. A block of RAM can be readily configured to function as a PAL with no additional array overhead. This PAL mode can be used for content addressable memory (CAM) type matching of input data against stored values.
OBJECTS OF THE INVENTION
It is therefore a principal object of the present invention to provide an FPGA wherein bit lines used for programming control memory, are also used for routing or logic functions after device configuration is completed.
It is another object of the invention to provide a configurable logic device having control memory for programming the device, the control memory receiving bit and word signals over bit and word lines, the latter being configured for redundant use for routing and/or logic functions.
It is still another object of the invention to provide a configurable logic device wherein control RAM bit lines are used as routing and/or wire-OR functions.
It is still another object of the invention to provide a configurable logic device wherein control RAM bit and word lines are used to implement programmable array logic (PAL) functions.
It is still another object of the invention to provide a configurable logic device wherein control RAM bit and word lines are used to implement a Content Addressable Memory (CAM) mode.
REFERENCES:
patent: 4866432 (1989-09-01), Goetting
patent: 5099150 (1992-03-01), Steele
patent: 5162680 (1992-11-01), Norman et al.
patent: 5352940 (1994-10-01), Watson
patent: 5444393 (1995-08-01), Yoshimori
patent: 5465055 (1995-11-01), Ahrens
patent: 5473267 (1995-12-01), Stansfield
patent: 5563527 (1996-10-01), Diba
patent: 9604496.1 (1996-03-01), None
Xilinx, Inc. “The Programmable Logic Data Book,” Sep. 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
Betty Prince, “Semiconductor Memories,” copyright 1983, 1991, John Wiley & Sons, pp. 149-174.
Anthony Stansfield et al., “The Design of a New FPGA Architecture,” 1995, Computer Science 975.
Le Don Phu
Tokar Michael
Xilinx , Inc.
Young Edel M.
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