High-speed logic embodied differential dynamic CMOS true single
High-speed standard cells designed using a deep-submicron...
High-speed, state-preserving, race-reducing,...
High-throughput asynchronous dynamic pipelines
Hold-time latch mechanism compatible with single-rail to...
Hot-clock adiabatic gate using multiple clock signals with diffe
Hybrid data and clock recharging techniques in domino logic...
I/O block for high performance memory interfaces
Independent clock edge regulation
Initialization of floating body dynamic circuitry
Input buffer circuit with constant response speed of output...
Input buffer using a differential amplifier
Input circuit and semiconductor integrated circuit...
Input isolation for self-resetting CMOS macros
Input synchronization mechanism for inside/outside clock
Input transition detection circuit for zero-power part
Integrated circuit and circuit arrangement for converting a...
Integrated circuit clock driver having improved layout
Integrated circuit communication techniques
Integrated circuit devices having data buffer control...