Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-10-18
2002-02-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000, C326S121000
Reexamination Certificate
active
06344759
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is a dynamic logic circuit type called domino logic or precharge/conditional discharge logic.
BACKGROUND OF THE INVENTION
This invention concerns a problem with a dynamic logic circuit type called domino logic. In domino logic, a circuit node is charged to a precharge voltage during a precharge time. In the typical application, a P-channel MOSFET charges the circuit node to the supply voltage. During a evaluate phase, the precharging ceases. Instead a logic block conditionally discharges the circuit node. If the logic condition of the logic block is satisfied corresponding to a “1” output, then at least one conduction path is formed between the precharge node and ground. This conduction path discharges the charge on the precharge node reducing its voltage to near the ground potential. If the logic condition of the logic block is not satisfied corresponding to a “0” output, then no conduction path exists between the precharge node and ground. The logic block is typically constructed with one or more N-channel MOSFETs. Since the charge remains on the precharge node, its voltage does not change. At the end of the evaluate phase a sensing circuit, typically an inverter, senses the voltage on the precharge node and drives the output accordingly.
One of the good features of domino logic is the capability of forming arbitrarily complex logic terms in the logic block. The typical data processing apparatus will have at least some functions that require many logic terms having both AND and OR terms. Domino logic provides the opportunity to form complex logic functions within a relatively small logic block.
A problem exists with domino logic that inhibits its use to embody wide input AND gates. For AND gates the logic block is a cascade series of N-channel MOSFETs. The AND condition is satisfied only if all the N-channel MOSFETs are turned ON during the evaluate phase. Only then will a discharge path exist between the precharge node and ground. Wide input AND gates require a long chain of such N-channel MOSFETs. The problem with such domino logic is called charge sharing. When some but not all of the N-channel MOSFETs are ON, the charge on the capacitance of the precharge node is shared with all the parasitic capacitance of the thus connected intermediate nodes. This charge sharing reduces the charge on the precharge node and hence reduces its voltage. This voltage reduction due to charge sharing decreases the noise margin of the sensing circuit. In severe cases this charge sharing can so reduce the voltage that the sensing circuit senses the wrong condition and produces the wrong output. Note that this charge sharing problem is worse when all the chain of N-channel MOSFETs are ON except for the N-channel MOSFET nearest ground which is OFF. This worst case couples the maximum number of nodes to the precharge node without discharging the precharge node. Thus the charge on the precharge node must be distributed over the maximum capacitance, contributing to the maximum reduction in voltage when the precharge node is not discharged.
Wide input OR gates do not present a charge sharing problem. OR gates are typically implemented with parallel N-channel MOSFETs between the precharge node and ground. To satisfy the OR condition all the OR gates must be OFF. If any of the N-channel MOSFETs is ON, then the precharge node is discharged. No serial chain with additional nodes to share charge appear for OR gates. Thus OR gates are not a problem. Logic functions with both AND and OR terms may present a charge sharing problem depending on the number of AND terms.
One solution to this problem is to limit the number of AND terms evaluated by any particular gate circuit. Limiting the number of AND terms limits the number of nodes that may participate in charge sharing. This limitation then limits the voltage drop encountered during charge sharing, reducing the severity of the problem. The maximum length of serial chains which have no adverse charge sharing depends upon the circuit type. This maximum length serves as a design limit for that circuit type. If a logic operation requires an AND function having more terms than permitted by this design limitation, then additional gates are used. This has the disadvantage of increasing the gate depth, or the number of gates needed, to perform the logic function. Increasing the gate depth typically requires more circuits for the same function and requires more time to generate the result. This is disadvantageous. One advantage of domino logic is the capability of performing arbitrary logic functions in a single gate. Thus this disadvantage negates one rationale for employing domino logic.
It is known in the art to precharge an additional circuit node to reduce the problem with charge sharing. Typically the next node in the serial chain of N-channel MOSFETs is precharged at the same time as the precharge node. In this case, under conditions where charge sharing may be a problem, there is additional charge at this next node. With this additional charge in the serial chain of N-channel MOSFETs, the worst case amount of charge drained from the precharge node is reduced. As a consequence, the maximum voltage drop on the precharge node is reduced. This reduces the problem of charge sharing. It is known in the art to precharge plural intermediate nodes. This introduces a disadvantage when the precharge node is to be discharged because the logic condition is satisfied. The additional charge on the other node or nodes within the serial chain must also be discharged when all the N-channel MOSFETs are ON. Discharging the precharge node charge and this additional charge requires more time than discharging the precharge node charge alone. One advantage of domino logic is its speed of operation. Thus this disadvantage negates one rationale for employing domino logic.
SUMMARY OF THE INVENTION
This invention is useful in domino logic circuits. In domino logic circuits a precharge device precharges a precharge node during a precharge phase of a clock signal. A logic block receives plural input signals and conditionally discharges the precharge node. In this improvement, a second precharge device precharges an intermediate node when a particular input signal controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be an intermediate node nearest to the precharge node. Alternatively, the intermediate node may be any intermediate node including the last in a serial chain from the precharge node. The input signal controlling the second precharge device preferably controls a logic device last a serial chain from the precharge node. This second precharge device may be used with a third precharge device according to the known art which precharges the intermediate node during the precharge phase.
This domino logic circuit may be used with another precharge device controlled by a second input signal different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node.
If the input signal controlling the second precharge device is unconstrained, then it is not certain that the intermediate node will be precharged during the precharge phase. In that case, the circuit preferably includes a clock controlled precharge device operative during the precharge phase to precharge the intermediate node. The circuit also preferably includes a discharge control device disposed between said logic block and ground to isolate said logic block from ground during the precharge phase preventing discharge. This discharge control device is conducting during the evaluate phase to permit discharge of the precharge node. Alternatively, the input signal may be clocked and guaranteed low during the precharge phase. In this case the clocked precharge of the intermediate node is optional. In addition, the discharge control device may be omitted.
REFERENCES:
patent: 5146115 (1992-09-01), Benha
Bosshart Patrick W.
Ko Uming
Srivastava Pranjal
Brady III W. James
Chang Daniel D.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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