Input isolation for self-resetting CMOS macros

Details Input isolation for self-resetting CMOS macros Input isolation for self-resetting CMOS macros

1997-06-24

1999-08-17

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 98, H03K 1900, H03K 19096

Patent

active

059398981

ABSTRACT:
Very fast very large scale integrated (VLSI) chips can be built-up from "self-resetting" or "self-timed" macros. An input isolator circuit provides an effective input isolation/decoupling which allows the input pulse widths to vary over a wide range. This avoids, for a large chip having many macros, a significant problem in insuring that the output from one macro is compliant with the input requirements of a receiving macro. Mixed static and dynamic circuits are used. The circuit comprises three stages. The input first stage is a static NOR circuit providing a pulse-chopping function. This first stage chops any too wide input pulse to the desired pulse width. The middle stage is a self-resetting complementary metal oxide semiconductor (SRCMOS) dynamic NOR circuit to capture input which is reset too soon. The last stage is a half-latch circuit to keep the dynamic node at constant output voltage level. The interfaces of all self-resetting macros in accordance with the teachings of the invention have no need for a handshake circuit or interlock circuits.

REFERENCES:
patent: 5550490 (1996-08-01), Durham et al.
patent: 5565798 (1996-10-01), Durham et al.
patent: 5652530 (1997-07-01), Ashuri
patent: 5698996 (1997-12-01), Ko
patent: 5767715 (1998-06-01), Marquis et al.
patent: 5859547 (1999-01-01), Tran et al.

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