Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-12-15
2001-05-22
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S112000, C326S121000
Reexamination Certificate
active
06236240
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is logic circuits and more particularly hold-time latching in single-rail to dual-rail conversion dynamic logic circuits.
BACKGROUND OF THE INVENTION
Conventional dynamic logic provides excellent opportunities for significant performance improvement. Such dynamic logic often entails a number of special requirements which often can be met only at the expense of additional circuit complexity. This circuit complexity occasionally includes the expense of burdensome duplication of circuitry not ordinarily needed in logically equivalent static logic designs. For example, domino logic is the conventional form of dynamic logic being used in current dynamic logic designs. In domino logic, the implementation of non-unate logic, such as XOR logic, requires dual-rail signals. Such dual-rail signals clearly entail the generation of the often otherwise unavailable phase of the signal or signals. Because XOR gates are a reasonably common occurrence, the generation of dual-rail versions of signals is a frequent requirement and this is a more complex circuit function than the simple inversion used in static logic.
Other restrictions and drawbacks are encountered when a hold-time latch is required. Hold-time is defined as the amount of time for which a data signal must remain valid after the active clock edge has occurred or after the active clock time interval has begun for the case of dynamic logic, in order to obtain a valid logical result. In contrast to the register-based logic of static designs, domino logic uses a latch-based approach. A hold-time latch is commonly integrated into the consuming or receiving gate for best performance and circuit economy. This gives rise to special circuit considerations which must be considered to make the circuit function implementation successful.
SUMMARY OF THE INVENTION
The unique circuit of this invention provides a means of integrating two circuit functions in the same circuit block. These two circuit functions are hold-time latching and from single-rail logic signals to dual-rail logic signals. Moreover the circuit accomplishes this with minimal circuit complexity and provides high performance and reliable functionality. Because hold-time latching and conversion from single-rail to dual-rail are frequently recurring needs in domino logic, the circuit configuration of this invention will be widely used and will have a significant impact on future designs.
REFERENCES:
patent: 4668880 (1987-05-01), Shoji
patent: 4851714 (1989-07-01), Hwang
patent: 5208489 (1993-05-01), Houston
patent: 6124735 (2000-09-01), Blomgren et al.
Brady III W. James
Le Don Phu
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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