Integrated circuit and circuit arrangement for converting a...

Details Integrated circuit and circuit arrangement for converting a... Integrated circuit and circuit arrangement for converting a...

2005-09-20

2005-09-20

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S095000, C326S093000, C327S203000, C327S201000

Reexamination Certificate

active

06946878

ABSTRACT:
An integrated circuit that converts a single rail signal into a dual-rail signal includes a clock signal connection, a data input to which a single-rail signal is applied, a data output on which a dual-rail signal is tapped off on output lines, and a converter, which is connected between the data input and the data output, that converts the single-rail signal into the dual-rail signal. The converter includes a memory cell having an input connected to the data input and output connections, wherein in a transparent state, the output connections provide the logically valid dual-rail signal, and a circuit arrangement, which is arranged between the output connections of the memory cell and the data output of the integrated circuit, that precharges the output lines connected to the output connections, and ensures a direct transition from a precharge phase to a logic state on the output lines, and vice versa.

REFERENCES:
patent: 4149099 (1979-04-01), Nagami
patent: 4435791 (1984-03-01), Gingerich
patent: 4751681 (1988-06-01), Hashimoto
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5825224 (1998-10-01), Klass
patent: 5920218 (1999-07-01), Klass et al.
patent: 6081153 (2000-06-01), Hamada
patent: 6121807 (2000-09-01), Klass
patent: 6222404 (2001-04-01), Mehta et al.
patent: 6236240 (2001-05-01), Hill
Patent Abstracts of Japan, vol. 005, No. 153, Sep. 26, 1981 & JP 56 086527 A (NEC CORP), Jul. 14, 1981, abstract.

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