High-speed standard cells designed using a deep-submicron...

Details High-speed standard cells designed using a deep-submicron... High-speed standard cells designed using a deep-submicron...

2009-12-31

2011-10-11

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S021000, C326S022000, C326S026000

Reexamination Certificate

active

08035419

ABSTRACT:
A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.

REFERENCES:
patent: 6222410 (2001-04-01), Seno
patent: 6380764 (2002-04-01), Katoh et al.
patent: 6842045 (2005-01-01), Shimazaki et al.

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