Hot-clock adiabatic gate using multiple clock signals with diffe

Details Hot-clock adiabatic gate using multiple clock signals with diffe Hot-clock adiabatic gate using multiple clock signals with diffe

1995-11-21

1997-10-07

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 98, 326 21, 326121, H03K 19096

Patent

active

056752636

ABSTRACT:
A hot clock adiabatic gate, using CMOS technology, incorporates an ancillary transistor. The gate is energized by multiple clock signals of different phases to reduce power consumption. The output logic voltage of the gate can reach full-rail voltage by allowing the CMOS technology to discharge via the ancillary transistor. The hot clock adiabatic gate and associated ancillary transistor may be incorporated into various logic circuits, such as an inverter, a memory cell, a NAND gate, and a NOR gate. In one configuration, a CMOS inverter is controlled by four clock signals having four discrete phases. The CMOS inverter optimally includes a CMOS gate transistor pair wherein the semiconductor channels of two ancillary transistors are in series with the semiconductor channels of the CMOS gate transistor pair.

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Seitz et al, "Hot-Clock nMOS 1985 Chapel Hill Conference on VLSI", pp. 1-17.
Koller et al., "Adiabatic Switching, Low Energy Computing, and The Physics of Storing and Erasing Information", Aug. 5, 1992, pp. 1-5.

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