High-speed logic embodied differential dynamic CMOS true single

Details High-speed logic embodied differential dynamic CMOS true single High-speed logic embodied differential dynamic CMOS true single

1997-11-21

2000-05-30

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 17, 326113, 326121, H03K 19096, H03K 190948

Patent

active

060694955

ABSTRACT:
A differential true single phase latch and flip-flop designed to embody logic functions is described. The logic function embodied latch includes a first circuit branch including first input switching devices for receiving a first set of input signals which include input signals and their corresponding complements and for outputting a first output signal having a logic state representative of the results of a logic function performed on said first set of input signals and a second circuit branch including second input switching devices for receiving the complement of the at least two input signals and can include the at least two input signals and for outputting a non-inverted output signal. First and second input switching devices are configured so as to cause the latch to perform logic functions on the input signals and latch output states corresponding to the results logic functions on its non-inverted and inverted outputs in the same clock phase.

REFERENCES:
patent: 4570084 (1986-02-01), Griffin et al.
patent: 4620117 (1986-10-01), Fang
patent: 4716312 (1987-12-01), Mead et al.
patent: 5023480 (1991-06-01), Gieseke et al.
patent: 5841298 (1998-11-01), Huang

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