Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-09-08
1997-03-25
Hudspeth, David R.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
327292, 327298, H03K 1900
Patent
active
056148453
ABSTRACT:
A clock regulator that provides two controlled timing references per clock cycle on a single clock distribution. The regulator includes two phase detectors and phase aligner pairs to independently regulate both rising and falling edges of the clock distribution, rather than regulating only one edge as conventional regulators.
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Davis, Jr. Michael A.
Hudspeth David R.
International Business Machines - Corporation
Roseen Richard
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