Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-08-20
2001-05-15
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S113000
Reexamination Certificate
active
06232797
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 98-35854, filed Sep. 1, 1998, the disclosure of which is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to integrated circuits, and more particularly to synchronous integrated circuit devices having data buffers therein and methods of operating same.
2. Background of the Invention
Synchronous dynamic random access memory devices (SDRAMs) typically convert an external clock signal (CLK) into an internal clock signal (PCLK) that is used to control operation of internal circuits. In addition, an SDRAM device may include control clock generators that generate specialized control clock signals in response to the external clock signal. For example, a buffered output control clock signal (CLKDQ) may be generated in response to the external clock signal and used internally to control the operation of a data output buffer.
Referring now to
FIG. 1
, a data output buffer
130
and output buffer control circuit
110
of a conventional SDRAM are illustrated. The output buffer control circuit
110
receives a data latency signal LAT and generates an output control signal PTRST. A CMOS transmission gate
111
and inverter
112
are utilized to pass the latency signal LAT under the control of a buffered output control clock signal (CLKDQ). In particular, when the buffered output control clock signal CLKDQ transitions to a logic 1 level, the latency signal LAT passes through the transmission gate
111
and becomes latched by a pair of inverters
113
and
114
. An output inverter
115
is also provided.
The output control signal PTRST is provided as an input to the data output buffer
130
which comprises NAND gates
131
and
134
, inverters
132
,
133
and
135
, NMOS pull-up transistor
136
and NMOS pull-down transistor
137
. As will be understood by those skilled in the art, when the output control signal PTRST transitions to a logic 1 level, the data output buffer
130
becomes enabled and operates to pass a data on input/output signal line DIO to an output signal line DOUT. However, when the output control signal PTRST transitions to a logic 0 level, the data output buffer
130
becomes disabled and blocks passage of the data.
As described more fully hereinbelow with respect to
FIGS. 2-3
, the output control clock signal CLKDQ controls the timing of when the latency signal LAT is latched into the output buffer control circuit
110
and therefore controls the timing of when the data output buffer
130
is enabled to pass data or disabled to block data. For example, the timing diagram of
FIG. 2
illustrates the generation of an internal clock signal PCLK in-sync with an external clock signal CLK and the generation of the output control clock signal CLKDQ in-sync with the external clock signal CLK.
FIG. 2
also illustrates the generation of a latency signal LAT in response to the internal clock signal PCLK and the generation of the output control signal PTRST (and latching of the latency signal LAT) in response to the output control clock signal CLKDQ. Based on the configuration of the control circuit
110
, Thus, a trailing edge of the latency signal LAT (that is in-sync with a rising edge of the internal clock signal PCLK) may be latched by the output buffer control circuit
110
(when the output control clock signal CLKDQ is at a logic 1 level) and passed to the data output buffer
130
as a disabling output control signal PTRST.
Because the timing paths associated with the generation of the internal clock signal PCLK and the output control clock signal CLKDQ may be different, the timing of the latency signal LAT may not correspond closely with the timing of the output control clock signal CLKDQ. Accordingly, as illustrated by
FIG. 3
, a faulty or attenuated external clock signal pulse (point a) may trigger a correct internal clock signal PCLK pulse, but may not trigger a correct output control clock signal CLKDQ pulse (point b). If this occurs, the output control signal PTRST may not transition at point “c” to a logic 0 level to thereby disable the data output buffer
130
. In other words, the conventional SDRAM may be prone to malfunction in the event a faulty external clock signal is received by the SDRAM.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide circuits for controlling data buffers that can operate reliably even when clocking errors occur.
These and other objects, advantages and features of the present invention are provided by integrated circuit devices that may include a memory cell array and an output buffer that receives data from the memory cell array, via a data input/output signal line DIO. The output buffer passes the received data to a data output signal line DOUT under the control of an output control signal PTRST. The output control signal PTRST is generated by an output buffer control circuit. The output buffer control circuit comprises an output control signal generator and an automatic pulse generator. Both the output control signal generator and the automatic pulse generator are responsive to a latency signal LAT. The output control signal generator is also responsive to an output control clock CLKDQ and an automatic pulse signal PRECHDQ. The output control clock CLKDQ is generated by an output control clock generator and the latency signal LAT is generated by a latency signal generator. The latency signal generator is responsive to an internal clock generator that generates an internal clock PCLK. In addition, the output control clock generator and internal clock generator are responsive to an external clock signal CLK.
According to one aspect of the present invention, the output control clock CLKDQ and the internal clock signal PCLK and latency signal LAT derived therefrom are provided on separate timing paths. These different clock signal timing paths increase the likelihood that phase differences may occur between the internal clock signal PCLK and the output control clock CLKDQ. To inhibit the likelihood that a faulty external clock signal CLK will result in an inability to properly disable an output buffer, an automatic pulse generator is provided within the output buffer control circuit. The automatic pulse generator comprises a two-input NOR gate and an inverter chain that includes three inverters electrically connected in series. A trailing edge transition of the latency signal LAT (i.e., a 1→0 transition) will cause the NOR gate to generate a logic 1 pulse on the automatic pulse signal line PRECHDQ. The logic 1 pulse will also cause the control signal PTRST to be set to a logic 0 level, even if the output control clock is defective. This logic 0 output control signal PTRST will then operate to disable the output buffer in a proper manner.
REFERENCES:
patent: 4777623 (1988-10-01), Simazu et al.
patent: 4974241 (1990-11-01), McClure et al.
patent: 5146110 (1992-09-01), Kim et al.
patent: 5280203 (1994-01-01), Hung et al.
Choi Won-jae
Lee Jung-bae
Lee Si-Yeol
Myers Bigel & Sibley & Sajovec
Paik Steven S.
Samsung Electronics Co,. Ltd.
Tokar Michael
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