Integrated circuit clock driver having improved layout

Details Integrated circuit clock driver having improved layout Integrated circuit clock driver having improved layout

1994-03-21

1995-05-16

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326103, 257207, 257211, H03K 19094

Patent

active

054164311

ABSTRACT:
An application specific integrated circuit (ASIC) clock driver is built under the power supply second level (metal2) buses, with the p-channel and n-channel transistors lying under the V.sub.DD and V.sub.SS buses, respectively. The transistor gates in the clock driver are placed orthogonally with respect to the transistor gates in the polycells. This allows for easy access to the metal2 bus and eliminates the need for the clock driver transistors to "add to" the current flowing through the first level (metal1) V.sub.DD /V.sub.SS buses in the polycell row. Therefore, electromigration concerns are reduced for: (1) the core logic polycells; (2) within the clock driver itself; and (3) on the metallization of the output of the clock driver, since the clock driver typically drives large capacitive loads. The orthogonal layout scheme also allows for full contact of the transistors source and drain regions to the corresponding metal bus, providing for low series resistance. Individual clock drivers may be readily paralleled into a main clock driver in the same vertical section ("spine"), and more than one main clock driver may be placed in a spine.

REFERENCES:
patent: 4570176 (1986-02-01), Kolwicz
patent: 4740825 (1988-04-01), Saeki
patent: 4906872 (1990-03-01), Tanaka
patent: 4958092 (1990-09-01), Tanaka
patent: 5087955 (1992-02-01), Futami
patent: 5291043 (1994-03-01), Arakawa
patent: 5345098 (1994-09-01), Hirabayashi et al.
patent: 5355004 (1994-10-01), Saitoh
TI Design Manual for TGB1000/TEB1000 BICMOS Arrays, 1992, pp. 2-16 through 2-21 and 7-16 through 7-23.

Affiliated with

Also associated with

Rating

Integrated circuit clock driver having improved layout does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit clock driver having improved layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit clock driver having improved layout will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-640421