Glitch-free clock enable circuit
Glitch-free clock enable circuit
Global clock self-timed circuit with self-terminating...
Half-swing line precharge method and apparatus
Hi gain clock circuit
Hi gain clock circuit
Hierarchial clock distribution system and method
Hierarchical clock distribution system and method
High frequency clock signal distribution circuit with reduced cl
High performance clock-powered logic
High speed data bit latch circuit
High speed latch/register
High speed latch/register
High speed low power data transfer scheme
High speed multiple-bit flip-flop
High speed output enable path and method for an integrated...
High speed, low power CMOS logic gate
High voltage level translator
High-performance clock-powered logic
High-speed domino logic with improved cascode keeper