High speed data bit latch circuit

Details High speed data bit latch circuit High speed data bit latch circuit

2007-03-20

2007-03-20

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S044000, C326S096000, C327S217000, C327S218000

Reexamination Certificate

active

11163501

ABSTRACT:
A latching circuit having a clock signal input and a data input, includes an inverting delay circuit having an input connected to DATA IN and having an output signal s1, a NAND circuit having a first input connected to signal s1, a second input connected to the clock signal, and an output signal s2, an OR circuit having a first input connected to the data input, a second input connected to s2, and an output signal s3, and a FLIP-FLOP circuit whose first input is connected to s2, whose second input connected to s3, and whose output is OUT Q.

REFERENCES:
patent: 5557225 (1996-09-01), Denham et al.
patent: 2005/0001488 (2005-01-01), Yamada

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