Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2006-07-04
2006-07-04
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S093000, C326S113000, C327S202000, C327S208000
Reexamination Certificate
active
07071736
ABSTRACT:
A method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logical value on the line being precharged. In some embodiments, a driver circuit drives an output node either high or low during a first phase of each clock cycle, and a precharge circuit then precharges the output node to an intermediate voltage during a second phase of the clock cycle in preparation for the following clock cycle. Some embodiments include source-follower configured FETs to precharge, wherein these FETs turn off once the output voltage reaches an intermediate value.
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Cray Inc.
Lemaire Charles A.
Lemaire Patent Law Firm, P.L.L.C.
Tan Vibol
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