Global clock self-timed circuit with self-terminating...

Details Global clock self-timed circuit with self-terminating... Global clock self-timed circuit with self-terminating...

2000-06-30

2003-03-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C326S121000

Reexamination Certificate

active

06531897

ABSTRACT:

BACKGROUND
1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to high frequency integrated circuits that include domino logic.
2. Discussion of Related Art
Advances in semiconductor manufacturing technologies have enabled circuit designers to continue to integrate more transistors on a single die. At the same time, computer architecture, and more specifically, processor architecture, continues to focus on shorter and shorter cycle times.
Domino logic is frequently used in an effort to reduce power, die area and output capacitance as compared to static full complementary metal oxide semiconductor (CMOS) logic. The reduction in parasitic capacitance provided by domino CMOS logic permits higher speed and lower power operation.
As clock speeds continue to increase (and thus, cycle times continue to decrease) and/or where certain parts of a chip operate at a much higher frequency, limitations of conventional logic circuits, including conventional domino logic circuits, may prevent such circuits from operating properly at the higher clock speeds. Further, many conventional domino logic circuits operate using a two-phase clock. For very high operating frequencies, it may not be feasible to generate and distribute a two-phase clock due to noise, clock jitter and/or other issues.
Where a pulsed clock is used instead of a conventional two-phase clock, the logic may be more susceptible to functional errors due to race conditions making such circuits more difficult for design engineers to work with. Further, in a pulsed clock environment, circuit operation is typically triggered by a leading edge transition of the pulsed clock signal. It may be desirable in some cases to ensure overlap of signal trailing edges to provide for proper operation of the circuit.
In some cases, to synchronize edges of intersecting signals, a global domino-type circuit may be used. A disadvantage of prior global domino circuits is that a reset device in the domino circuit is toggled regardless of whether or not an associated domino node has evaluated.
Some prior domino circuits may instead use one or more self-resetting gates. Such self-resetting gates have an advantage in that a precharge pulse will not be terminated unless the associated domino node is fully precharged. A disadvantage of such circuits, however, is that it may be difficult to intersect two signals because such circuits typically operate based only on the leading edge of a pulsed signal.


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