Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-02-17
2002-04-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S086000, C326S087000, C326S090000, C327S057000, C327S055000, C327S052000
Reexamination Certificate
active
06366130
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer scheme, and more particularly, to a high speed and low power CMOS data transfer scheme.
2. Description of the Prior Art
Today's requirements for electronic circuits require high speed. Additionally, the circuits should be as small and simple as possible due to the ever increasing number of circuits that arc crowding today's chip devices. Furthermore, circuits for data transfer should not be sensitive to circuit parameter mismatches, noise, and deviations in various applied voltages.
SUMMARY OF THE INVENTION
The present invention provides a high speed and low power CMOS data transfer arrangement that includes two active pull up/pull down bus drivers, a differential bus that precharges to a specific voltage level and a latched differential sense amplifier that serves as a bus receiver.
In accordance with one embodiment of the present invention, a data transfer arrangement includes two bus drivers, a voltage precharge source, a differential bus coupled to the bus drivers and to the voltage precharge source, and a latching sense amplifier coupled to the differential bus.
In accordance with another embodiment of the present invention, the latching sense amplifier is arranged as a cross coupled latched amplifier.
In accordance with a further embodiment of the present invention, the two bus drivers consist of active pull up/pull down bus drivers.
Thus, the present invention provides a data transfer arrangement that operates at a high speed and uses low power. The data transfer arrangement is faster because the bus voltage swing passes directly to high gain nodes of the cross-coupled latched amplifier. Additionally, the data transfer arrangement uses a lower number of stacked transistors coupled between the Supply voltage and the high gain nodes when compared to the prior art. Additionally, the arrangement according to the present invention is less sensitive to deviations in voltage sources and the deviation of threshold voltage concerns of the input transistors. Additionally, the arrangement is less sensitive to circuit parameter mismatches, data bus common mode noise and power bus noises.
Other features and advantages of the present invention will be understood upon reading and understanding the detailed description of the preferred embodiments below, in conjunction with reference to the drawings, in which like numerals represent like elements.
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Article “On the Parallel Evaluation of Polynomials” in IEEE Transactions On Computer, vol. C-22, No. 1, Jan. 1973 by Kiyoshi Maruyama.
Malshin Alexander V.
Podlesny Andrew V.
Solomatnikov Alexander Y.
Elbrus International Limited
Tan Vibol
Tokar Michael
Townsend and Townsend / and Crew LLP
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