Hi gain clock circuit

Details Hi gain clock circuit Hi gain clock circuit

2000-09-27

2003-04-15

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S083000, C327S142000, C327S198000

Reexamination Certificate

active

06549039

ABSTRACT:

BACKGROUND
1. Field
This invention relates to logic circuits, and more specifically to clock logic circuits with hi gain.
2. Background
A significant number of processing devices use clock logic in their circuitry. The clocks from the clock logic may be generated or buffered by clock logic circuitry contained as a part of the processing device, or exterior to the processing device. Depending on the specific design of this clock circuitry, the gain (e.g., output load/input load) produced at the clock circuit output with respect to the input to the clock circuit may vary.
FIG. 1
shows an example simple clock buffer circuit. This circuit is composed of an inverter gate
10
that receives a clock input and passes this onto a second inverter gate
12
. The size of inverters
10
and
12
may have been determined by the designer of this circuit so that the circuit achieves a particular gain. Gain is defined as the capacitance out of the circuit divided by the capacitance coming into the circuit and relates to the amount of load being driven by the output of the circuit as compared with the load at the input to the circuit. The size of inverters
10
and
12
are usually determined to achieve a given timing specification and, therefore, achieve a specific gain. For example, a typical gain for the circuit of
FIG. 1
may be gain=14.
FIG. 2
shows an example clock circuit that has been designed to produce a desired clock output waveform. In this circuit, inverter
10
receives a clock in just as in FIG.
1
. The output of inverter
10
is connected to a second inverter
14
and a NAND gate
18
. The output of inverter
14
is connected to a third inverter
16
, whose output is connected to a second input of NAND gate
18
. The output of NAND gate
18
produces the desired clock output waveform.
The design of the clock circuit shown in
FIG. 2
produces a clock output signal that transitions from a logic ‘0’ to a logic ‘1’ two inverter device delays after the clock input transitions from a ‘0’ to a ‘1’. Further, the clock output transitions from a logic ‘1’ to a logic ‘0’ four inverter device delays after the input clock transitions from a ‘1’ to a ‘0’. In the circuit of
FIG. 2
, with the load on the output of NAND gate
18
being the same as the load on the output of inverter
12
in
FIG. 1
, the gain of the circuit shown in
FIG. 2
is approximately equal to ten. The clock circuit shown in
FIG. 2
produces a clock that may be used in circuits such as domino logic circuits that may require a clock signal with these properties. Note that the gain of the circuit shown in
FIG. 2
has degraded as compared with that of FIG.
1
. This is because NAND gate
18
is less efficient in that it has a bigger input capacitance, thus causing the circuit of
FIG. 2
to achieve only a gain equal to ten. However, since in this example the inverter gates in
FIG. 2
are approximately the same size as those shown in
FIG. 1
, the circuit in
FIG. 2
actually takes up more space than the circuit in
FIG. 1
while producing less output gain.
Therefore, a need exists for a clock circuit for domino logic and other logic that produces the same function (i.e., clock output waveform) for a given load as the circuit in
FIG. 2
, but achieves high gain while occupying a minimum amount of space.


REFERENCES:
patent: 5467037 (1995-11-01), Kumar et al.
patent: 5796282 (1998-08-01), Sprague et al.
patent: 6011410 (2000-01-01), Kim et al.

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