High-speed domino logic with improved cascode keeper

Details High-speed domino logic with improved cascode keeper High-speed domino logic with improved cascode keeper

2005-06-14

2005-06-14

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S096000, C326S097000, C326S098000

Reexamination Certificate

active

06906556

ABSTRACT:
A high-speed domino logic with improved cascode keeper circuit uses an inverter delay element and an additional transistor to introduce a transition delay time and node isolation time to avoid the contest or “fight” between a first node and the keeper transistor in the event of a path to ground being created through the logic block portion of high-speed domino logic with improved cascode keeper circuit. The high-speed domino logic with improved cascode keeper circuits of the invention, in contrast to prior art domino logic circuits, can be designed to have high noise immunity and increased speed. In addition, since according to the invention, only a minimum of one new inverter and one new are required, the modification of the invention is space efficient and readily incorporated into existing designs.

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Won et al., “Modified Half Rail Differential Logic for Reduced Internal Logic Swing”, IEEE 0-7803-4455-3/98, 1998, pp. II-157 to II-160.
Kong et al., “Charge Recycling Differential Logic (CRDL) for Low-Power Application”, IEEE Journal of Solid-State Circuits, vol. 31, No. 9, Sep. 1996, pp. 1267 to 1276.

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