High voltage level translator

Details High voltage level translator High voltage level translator

2006-03-28

2006-03-28

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S068000, C326S095000, C327S333000, C327S111000

Reexamination Certificate

active

07019560

ABSTRACT:
A circuit for controlling a piezoelectric transducer includes an N-channel FET having a gate electrode, a drain electrode coupled to a high voltage signal source Vpp, wherein Vpp is a positive going pulse train, and a source electrode coupled to an output Vcntrl for controlling the transducer and a charging circuit, responsive to a low voltage input signal Vpp_sel, for charging the FET gate to a bias voltage greater than the FET's threshold voltage while Vpp is near zero volts and for maintaining the bias voltage on the FET gate while Vpp ramps up to a value greater than the bias voltage and until Vpp_sel is removed. The control circuit reduces switching time and reduces current spikes in the power supplies to the chip.

REFERENCES:
patent: 5263173 (1993-11-01), Gleason
patent: 5502468 (1996-03-01), Knierim
patent: 5867049 (1999-02-01), Mohd

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