Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1998-12-17
2001-09-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S113000, C326S098000
Reexamination Certificate
active
06285216
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
The present invention is related to the subject matter disclosed in U.S. patent application Ser. No. 09/164,661 filed on Oct. 1, 1998 for “Synchronous Integrated Circuit Device Utilizing an Integrated Clock/Command Technique” assigned to United Memories, Inc., Colorado Springs, Colorado and Nippon Steel Semiconductor Corporation, Tateyama, Japan, assignees of the present invention, the disclosure of which is herein specifically incorporated by this reference.
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices. More particularly, the present invention relates to integrated circuit devices, for example, asynchronous and synchronous dynamic random access memory (“DRAM”) devices, for which a fast data access is needed in conjunction with a pipelined data architecture.
Current integrated circuit devices tend to incorporate an excessive number of gate delays in their output data paths through the inclusion of a number of multiplexers deemed necessary to achieve acceptable levels of multiplexing. Moreover, such devices also tend to include extremely complicated anticipatory clock circuits implemented as phase locked loops (“PLLs”), delay locked loops (“DLLs”), time delay mirrors (“TDMs”) and the like which must be implemented in order to achieve the overall desired device speed. Since most current integrated circuit devices do not provide for a minimum clock cycle, the on-chip area required to support such anticipatory clock circuits is prohibitively large. Still other devices attempt to speed up the output data path by “over-driving” the associated circuit nodes which is also done at the expense of device power and on-chip area constraints.
SUMMARY OF THE INVENTION
The technique disclosed herein is a particularly efficient device logic approach which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and most amplification is added in the reset path which is not critical to access time. The output clocking technique of the present invention, particularly when integrated with the clock/command technique disclosed in the aforementioned patent application, eliminates most of the critical race and/or data overlap conditions within an integrated circuit.
Based on an external clock, several “one-shot” internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented in the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.
Stated another way, the present invention advantageously provides for a set of parallel output enable clocks, each of them implementing a “one-shot” clock embedded in the reset path of the output enable clocks, to provide the information necessary such that the next clock will also complete any data multiplexing functions that need to be executed. The duty cycle of the output enable clocks is matched to that of the other commands executing in the device to minimize race conditions and possible data overlap in the data path pipeline. The reset edge of the output enable clock is only derived from the buffered reset version of the main clock. Thus, the main clock only drives the active edge of the output enable clock. This significantly reduces the loading (or “fanout”) on the main clock. In addition, the main clock is not distributed to all the device output buffers with only the derived output enable clocks being distributed.
Particularly disclosed herein is an output enable circuit for an integrated circuit device wherein the circuit comprises a clock buffer for receiving an external clock signal and producing an internal clock signal displaced from the external clock signal by a delay imposed by the clock buffer circuit. A reset circuit is coupled to the clock buffer circuit for producing a reset clock signal displaced from the internal clock signal by a delay imposed by the reset circuit. At least one output enable logic circuit is coupled to receive the internal and reset clock signals, the output enable logic circuit producing an output enable -clock signal having a first state thereof initiated on a first logic level transition of the internal clock signal and a second state thereof initiated on an opposite second logic level transition of the reset clock signal. At least one pass gate is coupled to receive the output enable clock signal and a data signal and is operative to provide the data signal to an output node when the output enable clock signal is in the first state thereof.
Further disclosed herein is a process for multiplexing data from multiple data sources to a common output node on an integrated circuit device. The process comprises: supplying an external clock signal to the integrated circuit device; buffering the external clock signal to provide an internal clock signal having n gate delays; delaying the internal clock signal to provide a reset clock signal having (n+an odd number) additional gate delays; producing at least one output enable clock signal having a first state thereof initiated on a first logic level transition of the internal clock signal and a second state thereof initiated on an opposite second logic level transition of the reset clock signal; and passing data corresponding to one of the data sources to the common output node in response to the output enable clock signal being in the first state thereof.
REFERENCES:
patent: 6201413 (2001-03-01), Faue
patent: 06076592-A (1994-03-01), None
Faue Jon Allan
Meadows Harold Brett
Chang Daniel D.
Hogan & Hartson LLP
Kubida William J.
Tokar Michael
United Microelectronics Corporation
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