Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-06-07
1996-07-16
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
327141, H03K 19096
Patent
active
055370624
ABSTRACT:
A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock signal. The circuit receives an input clock signal and an input clock enable signal. The circuit generates an output clock signal which is an enabled/disabled version of the input clock signal, controlled by the input clock enable signal. The circuit thus provides the operational advantages of enabling or disabling, with a single control signal, groups of logic circuits triggered by a common clock signal.
REFERENCES:
patent: 4105980 (1978-08-01), Cowardin et al.
patent: 5083049 (1992-01-01), Kagey
patent: 5315181 (1994-05-01), Schowe
patent: 5379325 (1995-01-01), Katayama et al.
patent: 5387825 (1995-02-01), Cantrell et al.
patent: 5388225 (1995-02-01), Cantrell et al.
AST Research Inc.
Driscoll Benjamin D.
Westin Edward P.
LandOfFree
Glitch-free clock enable circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Glitch-free clock enable circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Glitch-free clock enable circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1787276