Hierarchial clock distribution system and method

Details Hierarchial clock distribution system and method Hierarchial clock distribution system and method

1996-08-28

1997-11-11

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

327297, 327293, 326101, H03K 1900

Patent

active

056868456

ABSTRACT:
A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.

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