High speed, low power CMOS logic gate

Details High speed, low power CMOS logic gate High speed, low power CMOS logic gate

2007-10-23

2007-10-23

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S098000, C365S203000

Reexamination Certificate

active

11207806

ABSTRACT:
A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher threshold voltage devices in other portions of the gate (e.g., precharge circuitry). This use of dual threshold voltage devices minimizes power consumption while maximizing speed. During standby mode, the gate is operated in an evaluation mode to substantially mitigate standby current.

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