ECL/TTL-CMOS translator bus interface architecture

Edge defined output buffer circuit

Edge detection using dual trans-impedance amplifier

Edge detector circuit and oscillator using same

Edge integrating phase detector

Edge programmable timing signal generator

Edge rate controlled output buffer circuit with controlled charg

Edge sense latch

Edge sensitive level translating and rereferencing CMOS circuitr

Edge sensitive set-reset flip flop

Edge sensitive single clock latch apparatus with a skew compensa

Edge set/reset latch circuit having low device count

Edge triggered clock distribution system

Edge triggered D-type flip-flop scan latch cell with recirculati

Edge triggered flip flop with multiple clocked functions

Edge triggered tri-state output buffer

Edge-rate feedback CMOS output buffer circuits

Edge-sensitive pulse generator

Edge-triggered flip-flop

Edge-triggered latch circuit conforming to LSSD rules