Edge sensitive level translating and rereferencing CMOS circuitr

Details Edge sensitive level translating and rereferencing CMOS circuitr Edge sensitive level translating and rereferencing CMOS circuitr

1987-05-26

1988-12-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307360, 307291, H03K 19094

Patent

active

047942835

ABSTRACT:
A logic level translator circuit includes capacitive coupling to facilitate rereferencing and differentiating of input logic signals. An input amplifier having complementary devices is responsive to the differentiated signals to provide control signals to a feedback circuit which holds one of the devices in a conductive state and the other in a non-conductive state to provide an output signal having predetermined logic levels. Threshold voltage generating circuits biases each of the devices.

REFERENCES:
patent: 4295057 (1981-10-01), Hendrickson
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4490633 (1984-12-01), Noufer et al.
patent: 4504747 (1985-03-01), Smith et al.
patent: 4578601 (1986-03-01), McAlister et al.
patent: 4593212 (1986-06-01), Svager
patent: 4636654 (1987-01-01), Lach

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