Edge-rate feedback CMOS output buffer circuits

Details Edge-rate feedback CMOS output buffer circuits Edge-rate feedback CMOS output buffer circuits

1991-03-07

1992-06-09

Mis, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307263, 307572, H03K 1716

Patent

active

051210002

ABSTRACT:
A CMOS output buffer circuit for providing an output signal at an output terminal which has a significant reduction in ground bounce over processing and power supply variations includes an output driver stage (12), a pull-up pre-driver circuit (14), a pull-down pre-diver circuit (16), and feedback means. The output driver stage is formed of a pull-up transistor (P1) and a pull-down transistor (N1). The feedback means is responsive to the output signal for controlling the rate of rise of the voltage at the gate electrode of the pull-down transistor so as to slow down its turn-on time when the output terminal is making a high-to-low transition, thereby significantly reducing the ground bounce. The feedback means is preferably formed of a capacitor (C2) having a first plate connected to the output terminal and a second plate coupled to the gate electrode of the pull-down transistor.

REFERENCES:
patent: 4906867 (1990-03-01), Petty
patent: 4961010 (1990-10-01), Davis
patent: 5028818 (1991-07-01), GoAng et al.

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