Edge defined output buffer circuit

Details Edge defined output buffer circuit Edge defined output buffer circuit

1980-05-14

1983-04-05

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307473, 307583, H03K 17693, H03K 19096

Patent

active

043792413

ABSTRACT:
A three-state MOS circuit for buffering an input signal includes an edge definition circuit which is controlled by first and second independent clock signals. The edge definition circuit includes a first transistor for producing a low-to-high voltage transition when the input signal goes from a high to a low, and a second transistor for producing a high-to-low voltage transition in response to the input signal going from a low to a high. The generation of these high-to-low and low-to-high transitions are controlled by first and second independent clock signals. The output of the edge definition circuit is applied to a driver circuit which generates output control signals. The output control signals are applied to first and second output field effect transistors so as to generate a signal representative of the input signal. The circuit is also provided with means for receiving a three-state control signal, which means is controlled by a third clock signal for disabling the driver portion of the buffer circuit so as to render the circuit output floating.

REFERENCES:
patent: 3935475 (1976-01-01), Margolies
patent: 3942037 (1976-03-01), Mensch, Jr.
patent: 4224533 (1980-09-01), Lai
patent: 4287442 (1981-09-01), Spinks et al.
patent: 4317053 (1982-02-01), Shaw et al.

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