Edge sense latch

Details Edge sense latch Edge sense latch

1979-02-26

1981-09-01

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307246, 307247R, 307279, H03K 5153, H03K 3356

Patent

active

042874424

ABSTRACT:
An MOS logic circuit is provided which generates and latches an output signal at a given logic level upon detection of a given transition in an input signal coinciding with a given state of a clock signal. The circuit utilizes the capacitance inherent in an MOS structure. The circuit requires a minimum of MOS components and is therefore useful in high density MOS integrated circuits where it is desired to detect and latch a transition in a signal.
The edge sense latch comprises an MOS inverter (Q1, Q2) responsive to an input signal S, a transmission gate (Q3) controlled by a clock signal, a transmission gate (Q4) controlled in part by an inherent capacitance (29), a latch comprising a pair of cross-coupled MOS transistors (Q5, Q8) for generating an output signal Q, and an MOS transistor (Q6) responsive to a reset signal R.

REFERENCES:
patent: 3921011 (1975-11-01), Orgill
patent: 3976949 (1976-08-01), Hepworth et al.
patent: 4082966 (1978-04-01), Lou
patent: 4112296 (1978-09-01), Heimbigner et al.
patent: 4224533 (1980-09-01), Lai

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