Edge triggered tri-state output buffer

Details Edge triggered tri-state output buffer Edge triggered tri-state output buffer

1991-09-16

1993-05-11

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, H03K 1900, H03K 1716

Patent

active

052104494

ABSTRACT:
A tri-state circuit is provided having first and second input lines for each receiving an input signal thereon. A circuit output line is connected to and controlled by an output switching circuit. A control circuit is responsive to both input signals to cause the switching circuit to adopt one of three states wherein the switching circuit delivers a high logic signal to the output line in a first state, a low logic signal in a second state, and no output signal in a third state. The circuit includes circuitry connected to the switching circuit and the output line for reducing the current in the output line to substantially zero over a transient period when the switching circuit is in the third state. The control circuit further includes a delay circuit for substantially reducing the transient period thereby minimizing the amount of current flowing in the output line when the circuit is in the third state.

REFERENCES:
patent: 4529895 (1985-07-01), Garverick et al.
patent: 4570091 (1986-02-01), Yasuda et al.
patent: 4777389 (1988-10-01), Wu et al.
patent: 4933579 (1990-06-01), Isobe et al.
patent: 5047673 (1991-09-01), Kaneko

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