Edge sensitive single clock latch apparatus with a skew compensa

Details Edge sensitive single clock latch apparatus with a skew compensa Edge sensitive single clock latch apparatus with a skew compensa

1984-07-02

1987-09-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307445, 307480, 328 63, 371 25, H03K 1900, H03K 1902, H03K 513

Patent

active

046926330

ABSTRACT:
A latch circuit possesses a scan capability, has a single clock input line, and possesses a locking feature whereby input data, once locked in the latch, is insensitive to further changes in state of the input data. The latch also possesses a novel selection apparatus which functions to select either a scan data input line or a system data input line in accordance with the binary state of a system gate input line, the selection apparatus developing an output signal, the binary state of which is locked in the latch in response to a predetermined state of a clock pulse conducted via the single clock line. Clock skew compensation is provided via the locking feature. During a scan mode, clock skew compensation is provided when the clock pulse is received for a period of time after termination of reception of a scan pulse conducted via the system gate input line.

REFERENCES:
patent: 3679915 (1972-07-01), Kriger
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 4229699 (1980-10-01), Fussell
patent: 4277699 (1981-07-01), Brown et al.
patent: 4359718 (1982-11-01), Payen
patent: 4554466 (1985-11-01), Dillon
"Single Clock Shift Register Latch", T. W. Williams, IBM Technical Disclosure Bulletin, vol. 16, No. 6, Nov. 1973, p. 1961.
"D-Type Latch", Y. K. Puri et al., IBM Technical Disclosure Bulletin, vol. 24, No. 8, Jan. 1982, p. 4365.
"LSSD Compatible D-Function Latch", F. J. Canova et al., IBM Technical Disclosure Bulletin, vol. 25, No. 10, Mar. 1983, pp. 5196-5198.

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