LandOfFree - US Patents - Listing for Electrical computers and digital processing systems: support,Clock, pulse, or timing signal generation or analysis

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Multi-channel architecture with channel independent clock signal

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Multi-chip module smart controller

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing

Multi-function timer with shared hardware

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Multi-phase multi-access pipeline memory system in which the...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Multi-stage clock selector

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Multimode system for calibrating a data strobe delay for a...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing

Multinode computer system with distributed clock...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Multiple clock domain microprocessor

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Multiple clock domain microprocessor

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate

Multiple internal phase-locked loops for synchronization of chip

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing

Multiple timer architecture with pipelining

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Multiple transmit data rates in programmable logic device...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Multiprocessor, memory accessing method for multiprocessor, tran

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Network transceiver having circuitry for referencing...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Nibble de-skew method, apparatus, and system

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Nibble de-skew method, apparatus, and system

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing

Non-volatile memory based monotonic counter

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate

Obtaining a phase error of a clock signal

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies

Obtaining configuration data for a data processing apparatus