Multiprocessor, memory accessing method for multiprocessor, tran

Details Multiprocessor, memory accessing method for multiprocessor, tran Multiprocessor, memory accessing method for multiprocessor, tran

1999-07-13

2000-03-14

Coleman, Eric

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

710 58, 710 45, G06F 1200

Patent

active

060386746

ABSTRACT:
A multiprocessor in which a plurality of processors are connected via a system bus. The multiprocessor includes processor groups each having at least one processor, a main storage memory, a cache memory, a cache control unit, a directory memory, and a directory control unit. The directory control unit includes an invalidation command issuing unit that issues a cache line invalidation command to all reference designations stored in the directory memory in cache lines. Thus the device process time can be shortened by reducing the frequency that cache invalidation commands are issued from the cache memory.

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