Multi-stage clock selector

Details Multi-stage clock selector Multi-stage clock selector

2005-09-30

2008-10-07

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Multiple or variable intervals or frequencies

C713S400000, C713S503000

Reexamination Certificate

active

07434082

ABSTRACT:
A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages having at least a first stage and a last stage. The input to the first stage is the plurality of input clock signals. At least one stage is adapted to (i) receive a plurality of clock signals, (ii) drop at least the first or the last clock signal of the received plurality of clock signals, and (iii) output a reduced plurality of clock signals. The output of the last stage is the set of candidate clock signals.

REFERENCES:
patent: 5515403 (1996-05-01), Sloan et al.
patent: 5778217 (1998-07-01), Kao
patent: 6310498 (2001-10-01), Larsson
patent: 6901126 (2005-05-01), Gu
patent: 2001/0018751 (2001-08-01), Gresham
patent: 2002/0105386 (2002-08-01), Shastri

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