Multiple timer architecture with pipelining

Details Multiple timer architecture with pipelining Multiple timer architecture with pipelining

1996-11-08

1999-10-12

Butler, Dennis M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Counting, scheduling, or event timing

G06F 104

Patent

active

059648821

ABSTRACT:
A timer counter with multiple timers in a pipelined architecture in which the multiple timers are serviced in the pipeline. The timer counter includes a control unit having a first control section and a second control section for sequencing the servicing of each of the multiple timers in a pipeline. The first and second control sections provide a pipeline sequence of the total required service of the timer counter. The pipeline architecture allows the multiple timers to be serviced in a pipeline without increasing the overall number of clocks.

REFERENCES:
patent: 4214173 (1980-07-01), Popper
patent: 4741004 (1988-04-01), Kane
patent: 4845728 (1989-07-01), Truong et al.
patent: 5659720 (1997-08-01), Fiacco et al.
patent: 5664167 (1997-09-01), Pickett et al.
Hwang et al., Computer Architecture And Parallel Processing, 1984, pp. 145-151.

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