Multi-function timer with shared hardware

Details Multi-function timer with shared hardware Multi-function timer with shared hardware

2000-05-19

2001-12-25

Heckler, Thomas M. (Department: 2182)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Counting, scheduling, or event timing

Reexamination Certificate

active

06334191

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, generally, to digital processors, and more specifically, to a multi-function timer with shared hardware for microprocessor-based engine control applications.
Micro-sequencers have commonly been used to sequence through instructions and data for processor usage in a digital system, such as a computer-based system. A difficulty of multiple digital signal input/output functionality implemented by a single micro-sequencer has been the ability of the sequencer to process multiple inputs/outputs with a high degree of resolution. The resolution is generally limited by the instruction throughput of the sequencer coupled with the complexity of the input/output functions. This limitation may result in a latency to reacting to a new input/output events while processing the most current event.
Current systems have typically dedicated a single algorithm in hardware to a single pin in a digital system. Also, in order to utilize different algorithms on the same pin, some systems have stored all potential algorithms with a pin and selection of only one of the algorithms is assigned to the pin. One disadvantage with these systems is that only one algorithm may be utilized on the input/output data at the pin. In other words, in systems such as microprocessor-based engine control systems, separate, dedicated circuits are used to generate multiple timed output events on dedicated output pins, and to perform multiple input timing measurements on dedicated input pins. Disadvantages of such systems include limited design flexibility in terms of die size, pin usage and hardware. Also, another disadvantage is that there is wasted circuitry hardware in the case of multiple algorithms on a selected pin in that only one algorithm will be utilized.
SUMMARY OF THE INVENTION
It is, therefore, an object of the invention to provide a microsequencer design using shared hardware to generate multiple timed output events and to perform multiple input timing measurements on the input/output pins of the device.
According to the present invention, the foregoing and other objects and advantages are attained by a multi-function timer comprising a plurality of slots and a compute engine. Each of the slots represents one of a plurality of timing processes, and the compute engine includes a micro-sequencer and a processor. The microsequencer identifies a current slot and associated plurality of instructions representing a process, and is configured to serially sequence through each of the slots. The processor performs the functions of the instructions associated with each current slot. Further, each slot is configured to perform any one of the following timing processes: pulse width modulation, high speed input, high speed output, or delta time input.
One advantage is that the present invention is capable of generating multiple timed output events and performing multiple input timing measurements using shared hardware in a microsequencer design. Another advantage is that the present invention simplifies the design of the timer and provides more flexibility in pin usage. An additional advantage is that the multi-function timer minimizes the amount of software and hardware overhead required by the host processor for input/output functions.
Other objects and advantages will become apparent upon reading the following detailed description and appended claims and upon reference to the accompany drawings.


REFERENCES:
patent: 4712072 (1987-12-01), Kawanabe
patent: 5631592 (1997-05-01), Schwarz et al.
patent: 5799182 (1998-08-01), Gravenstein et al.
patent: 5812833 (1998-09-01), Goler et al.
patent: 5854922 (1998-12-01), Gravenstein et al.
patent: 5893928 (1999-04-01), Gravenstein et al.

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