Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2005-05-03
2005-05-03
Browne, Lynne H. (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S400000, C713S401000, C713S500000, C713S503000, C713S600000, C324S130000, C327S136000, C327S263000, C327S276000, C327S392000, C365S189011, C365S193000, C365S194000, C702S085000, C702S089000, C714S724000, C714S814000, C714S815000
Reexamination Certificate
active
06889334
ABSTRACT:
A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.
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Loyer Bruce A.
Magro James R.
Mehta Pratik M.
Advanced Micro Devices , Inc.
Browne Lynne H.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Nitin
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