Multi-channel architecture with channel independent clock signal

Details Multi-channel architecture with channel independent clock signal Multi-channel architecture with channel independent clock signal

1998-03-30

2000-04-25

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

G06F 104

Patent

active

060556447

ABSTRACT:
Described is a multi-channel architecture comprising a central master clock generator for generating a central master clock signal and a plurality of channels connectable with inputs or outputs of a device. The multi-channel architecture further includes a channel master clock gate assigned to a respective channel of the plurality of channels, for receiving the central master clock signal and for generating a channel clock signal from the central master clock signal. The multi-channel architecture can be used in a tester arrangement, and preferably in an IC tester. The described multi-channel architecture allows clock signals to be provided for each one of the channels independent of other channels, e.g. to apply a continuous clock signal in one channel while the clock signal in other channels might be changed, e.g. in order to receive new timing edges as references for testing a DUT.

REFERENCES:
patent: 4788492 (1988-11-01), Schubert
patent: 5377206 (1994-12-01), Smith
patent: 5654657 (1997-08-01), Pearce

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