Delay locked loop for an FPGA architecture
Delay locked loop for an FPGA architecture
Delay locked loop for an FPGA architecture
Delay locked loop for and FPGA architecture
Delay tuning to improve timing in multi-load systems
Deletion system and method for removing temporary timer...
Deriving clocks in a memory system
Detecting states of signals
Determination of frequency of timer ticks
Determining a time difference between first and second clock...
Determining cycle adjustments for static timing analysis of...
Determining the timing of a data signal
Deterministically handling asynchronous events in a time...
Device and method for characterizing signal skew
Device for controlling and/or monitoring external technical...
Device for monitoring the periodicity of the messages sent...
Device with a clock output circuit
Difference capture timer
Differential clocking for digital platforms
Digital bus synchronizer for generating read reset signal