Digital bus synchronizer for generating read reset signal

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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Details

C713S503000

Reexamination Certificate

active

06901526

ABSTRACT:
A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

REFERENCES:
patent: 5268932 (1993-12-01), Okuzono
patent: 5359636 (1994-10-01), Aoyama
patent: 5623644 (1997-04-01), Self et al.
patent: 5634043 (1997-05-01), Self et al.
patent: 5809257 (1998-09-01), Shibazaki
patent: 6279077 (2001-08-01), Nasserbakht et al.

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