Delay tuning to improve timing in multi-load systems

Details Delay tuning to improve timing in multi-load systems Delay tuning to improve timing in multi-load systems

1999-12-21

2004-02-10

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000

Reexamination Certificate

active

06691241

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to a high frequency shared bus multiprocessor system, and more particularly, to a method for coordinating timing of communications to allow for high frequency operation of the multiprocessor system.
BACKGROUND OF THE INVENTION
Integrated circuits can be connected to an external communication bus and traditionally include an output buffer. An output buffer is also referred to as a driver circuit. An output buffer is typically characterized by a delay time experienced from applying a clock signal to an input of the buffer until valid data is provided at an output. This delay time is often referred to as Tco (time from clock to output). The performance of an integrated circuit/communication bus is limited, among other things, by the variation in Tco. In general, if Tco is too long, then the system operating frequency is reduced to allow time for the driven output to arrive at a receiver connected to a remote end of the communication bus. If the delay is too short, the output may arrive at the receiver too quickly. Thus, variations in Tco need to be controlled to remain between the two limits imposed by the system and its design targets.
An output buffer that allows the output buffer delay time to be dynamically controlled would be advantageous. One application of such an output buffer would be a shared bus multiprocessor system. Output buffers that have a fixed delay time that are used in multiprocessor systems require that the multiprocessor system be designed with a limitation on the minimum amount of wire that can appear between neighboring processors. This wire is needed to maintain minimum delays between processors in order to meet predetermined hold times.
In another architecture, a network of “point-to-point” interconnections replaces the shared bus. However, this makes the architecture much more complex and has been difficult to implement in practice.
SUMMARY OF THE INVENTION
A shared bus multiprocessor system is provided. The system comprises a communications bus, a first processor, a second processor, and a clock. The first processor has a first output buffer that has a first output delay time. The second processor has a second output buffer that has a second output delay time. The second output delay time is less than the first output delay time. Finally, the clock provides a clock signal to the first and second processors, with the clock signal arriving at the second processor before the first processor.


REFERENCES:
patent: 4541100 (1985-09-01), Sutton et al.
patent: 5367526 (1994-11-01), Kong
patent: 6316961 (2001-11-01), Kanetani et al.

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