Determining cycle adjustments for static timing analysis of...

Details Determining cycle adjustments for static timing analysis of... Determining cycle adjustments for static timing analysis of...

2007-04-17

2007-04-17

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C703S019000, C716S030000

Reexamination Certificate

active

10690059

ABSTRACT:
Given two synchronous clocks which transact data from a transmitter element to a receiver element which are analyzed by static timing, the interval between the transmitting data launch clock edge and the receiving capture clock edge is adjusted from the clock waveforms provided in order to represent the worst case slack situation between these two clocks over time. The amount of this adjustment is determined without unrolling (enumerating) all possible launch/capture pairs for these clocks. The greatest common divisor (GCD) of a transmit clock frequency and a receive clock frequency is determined. An effective phase shift is determined by performing a MOD operation between the GCD and an offset of the transmitter and receiver clocks. An algorithm uses the GCD and effective phase shift to determine a launch/capture interval that corresponds to a critical slack condition.

REFERENCES:
patent: 5355321 (1994-10-01), Grodstein et al.
patent: 5771375 (1998-06-01), Mains
patent: 6115827 (2000-09-01), Nadeau-Dostie et al.
patent: 2003/0192020 (2003-10-01), Collins

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