Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-12-23
2003-01-21
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Reexamination Certificate
active
06510526
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of buses. More particularly, the present invention pertains to clock generation and recovery for a bus.
BACKGROUND OF TH INVENTION
Many systems have a bus including a set of transmission lines on which information and one or more clock signals are communicated between various circuits. For example, digital computers have a bus for communicating among circuits such as processors, memory, direct memory access controllers, graphics processors among many other circuits. The bus may include transmission lines for data, addresses, and a system clock. The clock signal on the system clock line provides a time reference by which circuits connected to the bus are synchronized. Keeping an accurate time reference influences the reliable transfer of information on the data and address lines and the reliable use of the bus by the various circuits connected to the bus.
Unfortunately, conventional clock signals may be 1) susceptible to many sources of error and 2) may contribute to the noise environment of the system. For example, most clock signals have a single-ended substantially square or trapezoidal shape that is characterized by a fundamental frequency (Fo), duty cycle, and edge rate. The nature and characteristics of the clock signals make them susceptible to a variety of undesirable effects produced by impedance discontinuities and noise, among other sources of error. Furthermore, the broadband or wide band characteristics of conventional clock signals may cause interference with other signals and devices in the system.
First, because of the shape of the signal, the signal typically has significant high frequency components which are higher in frequency than the fundamental frequency. Consequently, the signal may occupy a bandwidth that is five times to ten times the fundamental frequency. Unfortunately, transmission lines do not typically provide uniform transmission of the wide band of frequencies contained in the typical clock signal. For example, any type of impedance discontinuity is frequency dependent, causing signal integrity problems that add skew to the system. This problem may result in the improper latching of data causing improper operation.
Second, the clock signal is affected by skew/jitter that may result from power plane noise, simultaneous switching output noise coupling, and impedance mismatches in the transmission lines. The effects of these skew/jitter sources are difficult to reject at a receiver that receives a single-ended signal. The effects of these skew/jitter sources on the signal may lead to improper operation and lack of synchronization.
Third, conventional clock signals, such as substantially trapezoidal or rectangular waves, present a significant electromagnetic interference (EMI) problem because of the many harmonics contained in such signals. The presence of many harmonics with significant power creates fields that may undesirably couple various elements in a system or interfere with other signals in the system.
Since having a wide band clock signal causes problems in crossing impedance discontinuities, it would be advantageous to generate a clock signal that is less problematic when crossing impedance discontinuities. Additionally, since generating a single-ended signal is not effective for minimizing the effects of the skew/jitter sources, it would be advantageous to generate and recover a clock signal in a manner that would allow rejection of the effects of the skew/jitter sources. Furthermore, since the presence of many harmonics in a clock signal is undesirable, it would be advantageous to generate a clock signal which does not present a significant EMI problem.
SUMMARY OF THE INVENTION
According to an embodiment of the invention, a method for recovering a clock signal communicated on a system bus is described. The method includes receiving at a receiver a first signal having a first polarity and receiving at the receiver a second signal having an opposite polarity to the first signal. The method also includes generating at the receiver a first clock signal based upon the first signal and the second signal.
REFERENCES:
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patent: 4546486 (1985-10-01), Evans
patent: 5121411 (1992-06-01), Fluharty
patent: 5789988 (1998-08-01), Sasaki
patent: 5834980 (1998-11-01), Pitio et al.
patent: 6320921 (2001-11-01), Gu
Heckler Thomas M.
Kenyon & Kenyon
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