Determining a time difference between first and second clock...

Details Determining a time difference between first and second clock... Determining a time difference between first and second clock...

2005-05-18

2009-08-04

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S502000, C713S503000, C375S354000, C375S362000, C375S371000, C375S372000

Reexamination Certificate

active

07571338

ABSTRACT:
Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal associated with a second clock domain. The buffering of the data is associated with a buffering delay. Counting circuitry receives at a start count input a write timing signal associated with the first clock domain and with writing data to the buffer circuitry. The counting circuitry receives at a stop count input a read timing signal associated with the second clock domain and with reading data from the buffer circuitry. A count value accumulated between receiving the write timing signal and the read timing signal corresponds to the buffering delay. Control circuitry performs a control operation based on the count value.

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CPRI Specification V1.0; “Common Public Radio Interface (CPRI); Interface Specification;” Sep. 30, 2003; pp. 1-54.
International Search Report mailed Sep. 8, 2005 in corresponding PCT Application PCT/SE2005/000767.

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