Delay locked loop for an FPGA architecture

Details Delay locked loop for an FPGA architecture Delay locked loop for an FPGA architecture

2000-03-06

2004-04-06

Butler, Dennis M. (Department: 2185)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Reexamination Certificate

active

06718477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay locked loop (DLL). More particularly, the present invention relates to a DLL in a field programmable gate array (FPGA).
2. Background Art
With the advent of FPGA architectures having greater complexity, it is well understood by those of ordinary skill in the art that extensive digital systems can be implemented in FPGA devices. These FPGA devices may include many clockable elements such as D-Type flip flops and blocks of user assignable static random access memory (SRAM). The D-type flip flops and the user assignable SRAM in the FPGA device may either be synchronized to the same clock or to several different clocks. When a substantial number of these clockable elements are employed in a particular design, it is presently contemplated that a least one multi-level “clock tree” will be provided in the FPGA device.
Multi-level clock trees are circuit devices that are well known to those of ordinary skill in the art. Typically, in a multi-level clock tree, a single lock source will drive the inputs to several clock buffers in the clock tree. This is known in the art as fanout. When the fanout becomes too large the clock signal will become unacceptably degraded. Accordingly, the fanout that a single source is permitted to drive is limited. The amount of fanout permitted depends upon the design being implemented. By implementing large clock buffers, limitations on the size of the fanout can be ameliorated. However, problems other than clock degradation also occur with the use of clock trees.
When the devices being clocked from the clock buffers are located at varying distances from the clock buffer, the clock signal may become skewed due to the differing clock net lengths. One solution to this problem is to provide a systematic clock tree design by strictly controlling the clock net lengths. Another is to incorporate final stage clock buffers that are located physically close to the clock inputs being driven. It should be appreciated however, that when additional systematic clock tree levels are introduced, additional delay is inserted between an original clock source and the clock input lines leading to the clockable elements in the FPGA.
This delay shows up, from the FPGA users viewpoint, as a lengthening of the FPGA's “clock-to-out” delay and an increase in the “hold time” of the FPGA. If the clock-to-out delay becomes too great a portion of the clock period, the overall system performance may suffer because the clock period would have to be lengthened to compensate for the length of the clock-to-out delay. It should be readily appreciated that other timing problems may occur in a design implemented in the FPGA as a result.
It is therefore an object of the present invention to control the internal clock tree delay by setting the internal clock tree delay to an amount that is selected by a user.
It yet another object of the present invention to implement a delay lock loop (DLL) having a plurality of modes for output feedback of the clock distribution tree.
It is another object of the present invention to a flexible interface between a DLL and the clock distribution trees, clock pads and signals from within an FPGA.
It is yet another object of the present invention to provide reset and power down signals for a DLL and a DLL/locked signal from the DLL.
These and other objects and advantages of the present invention will be readily appreciated by those of ordinary skill in the art from the disclosure of the embodiments of the present invention made herein.
BRIEF DESCRIPTION OF THE INVENTION
According to the present invention, a delay locked loop (DLL) is employed in a field programmable gate array (FPGA) to align the active edge of a reference clock with a selected edge of a delayed clock, hereinafter referred to as the feedback clock. The reference clock may either be an internal or external clock signal, and the feedback clock is a clock signal that is derived from the reference clock signal, but has been delayed by some circuit in the FPGA, for example, a clock distribution tree. In the operation of the DLL, the feedback clock is further delayed until the selected edge of the feedback clock is aligned with, but trailing by one cycle, the active edge of the reference clock. According to various aspects of the present invention, the feedback path of the feedback clock may be programmably selected to align the feedback clock to the reference clock at selected circuit nodes in the FPGA for the purpose of either deskewing the feedback clock or providing a 0 ns clock-to-out for the reference clock.


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