Trace compression method for debug and trace interface...
Trace control circuit adapted for high-speed microcomputer...
Trace control circuit adapted for high-speed microcomputer...
Trace unit
Trace unit with a decoder, a basic-block cache, a...
Trace unit with a trace builder
Tracking multiple dependent instructions with instruction...
Tracking network contention
Tracking register usage during multithreaded processing...
Training line predictor for branch targets
Transaction redirection mechanism for handling late...
Transferring data in a parallel processing environment
Transitioning from instruction cache to trace cache on label...
Transmit scheduler for an asynchronous transfer mode network and
Transparent concurrent atomic execution
Transparent concurrent atomic execution
Transparent extended state save
Two dimensional addressing of a matrix-vector register array
Two dimensional addressing of a matrix-vector register array
Two modes for executing branch instructions of different...